An 8mW 50MS/s CT ΔΣ modulator with 81dB SFDR and digital background DAC linearization

The intention of this work is to realize a power and area-efficient 50MS/S ΔΣ modulator with an OSR of only 10, an effective linearization without DEM, and a very low power ELD compensation. This is achieved by using a digital DAC error estimation and correction, and a compensation for finite gain-bandwidth (FGBW) in all feedback amplifiers. A multi-bit 3
^rd
-order, mixed feedforward-feedback compensation is used, which avoids the second DAC, limiting the swing of the first opamp, while reducing the STF peaking compared to an all feedforward topology.