Estimating and enhancing the tolerance and yield for tunneling SRAM cells by simulation

As a novel implementation of the static random access memory (SRAM), tunneling SRAM (TSRAM) uses a resonant-tunneling-diode (RTD)-based monostable-bistable logic element (MOBILE) and features low standby power dissipation and high integration density. A major challenge in TSRAM's low-cost manufacture is the wide current variability associated with the RTD's. In this paper, we propose a Monte Carlo simulation method for estimating and enhancing the tolerance and yield for the TSRAM cells, based on the current-voltage characteristics of the RTD's and the load-line diagram of the MOBILE.