Vendor supplied development environments based HW/SW partitioning

This paper describes a software entity termed a Partitioner. The Partitioner is designed to take a set of basic code modules as an input and in the process of reconfiguring a heterogeneous hardware platform finds a spatial scheduling (assignment to different processing units) and temporal scheduling for these modules that will optimised the performance of the unit. The components of the Partitioner are concurrency analysis, dependency analysis, profiling and optimal mapping. The heterogeneous platform is represented by three different commercially available development environments representing a RISC processor, DSP and FPGA.