Using inverter structure for 2∼6GHz low power high gain low noise amplifier

This paper presents a resistive-feedback amplifier and resistive-feedback inverter. To achieve low power consumption and high gain, the proposed LNA utilizes a current-reused technique and a splitting-load inductive peaking technique of resistive-feedback inverter for input matching. This UWB LNA is implemented by TSMC 0.18μm CMOS technology. The minimum noise figure is 3.67 dB. The amplifier provides maximum gain (S21) of 18.5 dB while drawing 10.3 mW from 1.5-V supply. This chip area is 1.028 × 0.921 mm
²
.