A process technology for a 5-volt only 4 Mb flash EEPROM with an 8.6 UM2 cell

A single-transistor advanced contactless EEPROM (ACEE) array technology with an 8.6 μm
²
cell developed for a single-power-supply 5-V only 4-Mb flash EEPROM is described. This ACEE technology has 0.8 μm minimum lithographic feature sizes and a novel sublithographic remote tunnel diode structure. Low-voltage isolation between bitlines of the same cell has been achieved by diode isolation at an effective separation of 0.65 μm; the high-voltage isolation between bitlines of adjacent cells depends on LOCOS isolation. The integrated process flow has successfully merged both the ACEE array and process enhancements for 18-V operation (2.0 μm, 18 V N-channel, 15 V P-channel) into a core 5-V 0.8 μm CMOS process with silicided contacts. This cell has been demonstrated on a full-circuit 4-Mb flash EEPROM VLSI vehicle