Merged CMOS/bipolar current switch logic (MCSL)

A merged CMOS/bipolar current switch logic (MCSL) is presented. CMOS/ECL level conversion and logical operation are realized simultaneously. This circuit technique allows a supply voltage reduction to 3.3 V. A carry delay time of 150 ps/bit for a 4-bit BiCMOS full adder was measured. This is about five times faster than an optimized CMOS adder.<
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