Yield enhancement by tube redundancy in CNFET-based circuits

This paper analyzes the functional yield of CNFET based circuits when the metallic tubes are removed by extra processing steps. Functional yield for various gates is obtained through both Monte-Carlo (MC) simulations and analytical models. Tube Level Redundancy (TLR) is proposed to increase the functional yield of gates to an acceptable level when a large fraction of tubes are removed. Our results are very promising and indicate that when critical paths are considered, almost 100% yield can be achieved for relatively complex systems.