A novel low-power 64-point pipelined FFT/IFFT processor for OFDM applications

This paper presents a novel pipelined FFT/IFFT processor for OFDM applications. The proposed architecture employs a low-complexity complex multiplier and a constant complex multiplier to eliminate the need of ROM tables, thus consumes lower power than the existing works. Finally, this design spends about 33.6K gates, and the power consumption is about 9.8mW at 20MHz.