Performing fault simulation in large system design

This paper presents a methodology and supporting set of tools for performing fault simulation throughout the design process for large systems. Most of the previous work in fault simulation has sought efficient methods for simulating faults at a single level design abstraction. This paper has developed a methodology for performing fault simulation of design models at the architectural, algorithmic, functional-block, and gate levels of design abstraction. As a result, fault simulation is supported throughout the design process from system definition through hardware/software implementation. Furthermore, since the fault simulation utilities are provided in an advanced design environment prototype tool, an iterative design/evaluation process is available for system designers at each stage of design refinement. The two key contributions of this paper are: a fault simulation methodology and supporting tools for performing fault simulation throughout the design process of large systems; and a methodology for performing fault simulation concurrently in hardware and software component designs and a proof-of-concept implementation.