Modeling and Characterization of Overlapping Circular-Gate mosfet and Its Application to Power Devices

This paper introduces a high-density layout style named overlapping circular-gate transistor (O-CGT) that allows the overlapping of circular gates from neighboring cells. With reference to rectangular-gate transistors (RGTs), higher aspect ratio per active area can be achieved. Besides, stray junction capacitances are minimal, improving switching performance. The first-order model for the O-CGT aspect ratio is used to size high-current devices of nominal on-resistance/current rate of 3.3 Ω/10 mA and 20 mΩ/2 A at V
$_{\rm GS}$
= 4.5 V. These power transistors were prototyped according to a standard mixed-signal 0.35-μm CMOS process and, respectively, occupy 1410 μm
$^2$
and 0.541 mm
$^2$
, which represent an area saving of up to 60% as compared to RGTs of equivalent aspect ratio. Excellent fitting between O-CGT analytical and experimental data is attained. O-CGTs and RGTs exhibit very close I
$_{\rm DS}$
× V
$_{\rm GS}$
characteristics, with deviations limited to 0.8% and 5.36% on subthreshold and strong inversion regions, respectively. The O-CGT drain-source breakdown voltage is 8.91 V, slightly above RGT. The O-CGT topology represents then a good option in designing power stages in smart-power chips using planar fabrication processes.