A 20MHz bandwidth continuous-time ΣΔ modulator with jitter immunity improved full-clock period SCR (FSCR) DAC and high speed DWA

A 20 MHz bandwidth continuous-time ΣΔ modulator with third-order active-RC loop filter and 4-bit quantizer is implemented in a 0.13 μm CMOS process. The immunity to clock jitter is greatly improved by employing full clock period switched-capacitor-resistor (FSCR) DAC for feedback. A new data weighted averaging (DWA) technique is adopted to remove the timing bottleneck at 640 MHz clock frequency. The modulator achieves 63.9 dB peak-SNDR. Dynamic range is 68 dB and decreases by only 2.3 dB when RMS clock jitter is 15 ps. The power consumption is 58 mW from a 1.2 V supply.