A 31mA CMOS wideband BD-II B2&B3 mode receiver with 55dB gain dynamic range

A CMOS wideband receiver for BD-Π B2&B3 mode is presented. The chip demonstrates a noise figure of 4.0dB and a 2dB CNR desensitization point of 4dBm at 800MHz GSM blocker. Due to the optimized design of an ESD-protected LNA and a 1/f-noise-reduced high-LO-RF-isolation Mixer, the spurious level is suppressed below −113dBm referred to the RF input. The fractional-N ΣΔ synthesizer obtains LO phase noise of −92dBc/Hz@lKHz and −117dBc/Hz@lMHz, with the reference spurs are below −60dBc. The integrated 4
^th
-order LPF has tunable 7.5MHz/10MHz/15MHz corner frequency. The mixed-signal AGC loop, including 4-bit ADCs, variable gain amplifier and programmable amplifier, achieves 55dB gain dynamic range. The receiver consumes 31mA from a 1.8-V supply voltage while occupying a 5.5-mm
²
die area including ESD pads.