Design for improved NBTI reliability of CMOS digital IC

A methodology to mitigate the degradation of digital circuits due to negative bias temperature instability (NBTI) at the view of circuit topology has been put forward in this work. With this approach, simple and strengthened inverter, NAND gate and NOR gate are simulated, the results prove that the proposed strengthened topologies are available to improve NBTI reliability of CMOS digital IC, which is valuable for reliable design against NBTI.