Transformation techniques for high speed implementation of recursive loop algorithms

In digital communication systems, high speed transmission requires implementation of high speed digital circuits which include adaptive equalizers, encoders and other signal processing algorithms. This paper proposes several high level architectural transformations that can be used to design families of architectures for a given algorithm. It also deals with high-level algorithm transformations such as look ahead. It is applied to design pipelined adaptive digital filters and parallel recursive digital filters. The technique used here can be used for high speed, low area and low power implementations of DSP systems for various applications such as multimedia, wired and wireless communications. Examples of these algorithms are differential pulse code modulation (DPCM), adaptive differential pulse code modulation (ADPCM), decision feedback equalizers (DFE's). DSP algorithms are described using mathematical formulations at a higher level. The internal feedback in these structures makes it difficult to implement using either pipelining or parallel processing techniques. This paper proposes different computation approaches for quantization algorithms, which can be easily pipelined. These approaches are suitable for real time highspeed implementation of quantizer loop operations. The power consumption of the proposed systems is less by the use of tri-state buffers in the implementation.