Work-function engineering in gate first technology for multi-VT dual-gate FDSOI CMOS on UTBOX

For the first time, we demonstrate low-V
_T
(V
_Tlin
±0.32V) nMOS and pMOS adjusted in a gate first FDSOI technology by work-function engineering of TiN/TaAlN metal gates. Especially, for low-V
_T
pMOS, various Chemical-Vapor-Deposited TaAlN stacks with optimized Al concentration have been studied to finely tune the work-function above midgap while maintaining good reliability and mobility. Short channel performance of 500μA/μm I
_ON
and 245μA/μm I
_EFF
at 2nA/μm I
_OFF
and V
_DD
=0.9 V is reported on pMOS with a TaAlN gate. In addition, it is found that the combination of these two metal gates with either n- or p-doped ground planes below the Ultra-Thin Buried Oxide (BOX) can offer 4 different V
_T
from 0.32 V to 0.6 V for both nMOS and pMOS, demonstrating a real multiple-V
_T
capability for FDSOI CMOS while keeping the channel undoped and the V
_T
variability around A
_VT
=1.3mV.μm.