FPGA implementation of modified decomposition filter

In this paper, new area minimized architecture is proposed for median filters based on modified decomposition algorithm. The modified decomposition replaces the complexity of existing threshold decomposition algorithm such as complex comparators. The proposed algorithm works in two stages, decomposition and recombination. The proposed algorithm removes the need for 0 to 255 threshold gray levels for each input in the given 3×3 window by decomposing each pixel itself using the 255 column counter. Similarly the decomposed pixel is regrouped using 9 column counters. This architecture requires a less number of slices and look up table for its VLSI implementation. The proposed architecture implemented in the XC2S400-6Eft256 FPGA using xilinx compiler version 7.1i. The results prove that the proposed architecture requires less area, optimum speed and equal power than the existing architecture.