Process variations in sub-threshold SRAM cells in 65nm CMOS

In this paper the effects of process variations on SRAM cell are investigated. The SNM (static noise margin) changes due to the threshold voltage variations, is discussed in details. In addition, the effect of NBTI in sub-threshold SRAM design is presented. Simulation results shows the effect of process variation including mismatches on SRAM cell. The SNM is degraded by 35% for higher temperatures and low supply voltage applications. Process variation effects on SRAM cells are included. STM 65nm models are used for simulations.