Modeling time-triggered mechanisms using MARTE

In real-time and embedded systems, time is a very important feature, and time-triggered architecture is a strong candidate platform. However, because UML is built on event-triggered mechanisms, it is not suitable for time-triggered mechanisms. This paper introduces UML profile for MARTE, and presents some modeling mechanisms which describe the time-triggered features based on MARTE. Finally, the paper also elaborates on the application of these mechanisms through a real case.