A 3-GHz dual-modulus prescaler based on improved master-slave DFF

An integrated low-power 3-GHz dual-modulus prescaler (DMP) divided-by-32/33 with a great tolerance to the clock-edge is presented in this paper. A novel structure of CMOS MS-DFF (master-slave D flip-flop) is used in the asynchronous part of the prescaler. The DFF based on the structure can work well in the clocks with longer clock-edge and overcome general-fast-circuit's requirement of clock-edge. The proposed prescaler can work in a quasistatic mode so its power consumption can be reduced. The proposed prescaler is realized with a 0.18-µm CMOS technology. The ratio of the operation range (3.49 GHz) to the maximum operation frequency (3.5 GHz) achieves 99%.