On the design and analysis of quaternary serial and parallel adders

Optimization techniques for decreasing the time and chip area of adder circuits have been thoroughly studied for years mostly in binary logic system. In this paper, we provide the necessary equations required to design a full adder in quaternary logic system. We provide the design of a logarithmic stage parallel adder which can compute the carries within log
₂
(n) time delay for n qudits. At last, we compare the gate delays of full adder and logarithmic stage parallel adder with the help of mathematical expressions.