A fast locking digital phase-locked loop using programmable charge pump

A proposed fast locking digital phase-locked loop (DPLL) is designed and simulated in this paper. The proposed topology based on converting the difference between the input frequency and the output frequency into a 3-bit code. This code is used to control a programmable charge pump (PCP) output current. As the difference between the two frequencies decreases, the PCP output current decreases to obtain smooth PLL locking. As locking is achieved, the PCP operates with its conventional current. The proposed DPLL is designed using UMC 130nm CMOS process with a 1.2V power supply. It operates in the frequency range 250MHz-1.75GHz. Over this frequency range a locking time reduction in the range of 35.7%-66.6% was achieved compared with conventional DPLL.