A robust design of SRAM sense amplifier for submicron technology

SRAM sense amplifier plays a key role in memory design. With technology scaling to the nanometer, the device mismatch increases and the distribution effect induces unstable signal injection, thus affecting the reliability of memory system. This paper presents a new method for SRAM sense amplifier design. It incorporates reasonable delay between the passgate and enable signals to effectively mitigates the failure ratio and keep the ratio less sensitive to signal slope. The novel amplifier structure is both simple and easy to control. A reliable design is given by considering both intrinsic and extrinsic offsets with reasonable speed and power consumption. A failure ratio analysis is performed. The result is validated using UMC 65nm process model.