A 200MS/s 10-bit current-steering D/A converter with on-chip testbench

This paper presents a 10-bit 200MS/s CMOS current-steering digital-to-analog converter (DAC) with on-chip testbench. The proposed DAC adapts segmented architecture, composed of 6 MSBs unary and 4 LSBs binary-weighted cells. The measurement results show that the converter achieves a spurious-free dynamic range (SFDR) up to 78.7dBc. The full-scale output current is 20mA with 3V power supply for analog part, while the digital part of the chip operates at 1.8V. The DNL and INL are less than 0.07LSB and 0.15LSB respectively due to an improved current switching scheme. The active area of DAC core is 0.2mm
²
in a standard 1P-6M 0.18μm CMOS process.