40nm10T SRAM cell with independent SNM WM and suppress active and leakage power

As the MOSFET's channel length is scaling down, SRAM stability becomes the major concern for future technology. The cell becomes more susceptible to both process induced variation in device geometry and threshold voltage variability due to doping fluctuation in the channel region. In this paper, a novel highly stable 10T SRAM cell is proposed which eliminates read SNM during read and write operation The cell suppresses active power owing to avoid the half select cell bit line fighting power. It also can work at ultra-low-voltage sub-threshold operation due to transistor stacking in the Read path to reduce leakage.