An improved Phase/Frequency Detector and a glitch-suppression charge pump design for PLL applications

This paper presents an improved phase frequency detector (PFD) and a novel charge pump (CP) for phase locked loop (PLL) applications. The output signals of the proposed PFD have perfect symmetry with the additional four latches. Two small PMOS transistors and two inverters are added to work as level recovery to avoid the uncertain state of PFD when the circuit powers on. The proposed CP circuit employs two rail-to-rail OP amplifiers to minimize the mismatch between the charging and the discharging current, which minimizes the steady-state phase error in a PLL and reduces the reference spurs. Moreover, a simple but effective technique is proposed to suppress the glitches of the output current, which also decreases the level of reference spurs in a PLL and at the same time increases the dynamic range of the CP. A PLL adopting the proposed PFD and CP is fabricated in TSMC 0.13um 1.2V CMOS process, and test results indicate that the PLL can achieve −56dBc reference spur level.