Image filtering using partially and dynamically reconfiguration

Modular based partially and dynamically reconfigurable (PDR) FPGA system is an ideal solution for run-time image processing system which needs to change the function of the processing unit dynamically. Here we present a new PDR image filter based on our self-developed FDP FPGA Device. In this system, the transition bus (TB) structure is proposed for physical separation of the static/dynamic blocks as required in PDR system. And we demo the system with an image filter aimed at filtering out mix-noise. The experiment results show that the proposed PDR system meets the requirement of the run-time image filter by its flexibility, fast reconfiguration speed, and saving of logic resource.