6/spl times/6 DPCNN: a programmable mixed analogue-digital chip for cellular neural networks

The implementation of a versatile VLSI chip represents an important step to develop cellular neural networks (CNN). In this paper a VLSI realization of the multi-chip oriented, 6/spl times/6 digitally programmable cellular neural network (6/spl times/6 DPCNN) chip, is presented. This chip covers most of the available one-neighbourhood templates for image processing applications. Moreover, it can be easily interconnected to others to form very large CNN arrays.