A 12bit 100MSps pipelined ADC without calibration

A 1.8V 12bit 100MS/s pipelined ADC in 0.18um CMOS process is presented. The first stage adopts 3.5-bit structure to relax the capacitor matching requirements. Bootstrapped switch and scaling down technique are used to improve the ADC's linearity and save power dissipation respectively. With a 2.4 MHz input signal, the ADC achieves 68.9dB SFDR and 9.3 ENOB at 101MS/s. The power consumption is 180mW at 1.8V supply including output drivers. The chip area is 3.51 mm
²
including pads.