Thermal modeling for advanced high power packaging development and on-line performance monitoring

As the market demands for high power and high efficiency power electronics, the industries has developed advanced IC technology and conceptual configuration. However, in order to guarantee the performance and reliability of the power electronics, the challenge of the packaging arises. This paper will use the thermal measurements and finite element method to describe the thermal impact of the geometric unflatness and imperfection of packaging process. The results show that the unflatness of the package substrate impacts the thermal performance. The thinner the die, the more sensitive the process imperfection (voids at die attach layer) is. Afterwards, we apply the concept of Design for Testability (DfT), and a potential online quality control method for the power electronic manufacturing is used and the method to obtain the testing parameter is proposed.