An empirical study of performance and power scaling of low voltage DDR3

Memory power consumption has become a main driving force of new memory technologies. Low voltage DDR3 (DDR3L) has emerged to provide optimal solution for performance and power for certain market segments. With empirical data, this paper demonstrates the scaling of DDR3L signal integrity performance and power consumption at full system level. The signal integrity performance is degraded by 10∼20% in terms of voltage and timing margin with strong DRAM vendor sensitivity. The DRAM power consumption is reduced by ∼20%. The impact to mobile notebook average and self-refresh power is also examined.