High-speed and low-power on-chip global link using continuous-time linear equalizer

A new equalized on-chip global link structure is proposed for ultra-high-speed and low-energy communication by utilizing continuous-time linear equalizer (CTLE). Modeling and optimization approaches for each building block are introduced and a low-power driver-receiver co-design methodology is proposed to greatly reduce energy-per-bit by 50%. Final design can achieve 20 Gbps signaling over 10 mm, 2.2 um-pitch on-chip T-line with 11 ps/mm latency and 0.19 pJ/b energy in 45 nm CMOS.