Characterization and Design of Through-Silicon Via Arrays in Three-Dimensional ICs Based on Thermomechanical Modeling

A general approach has been proposed for predicting the temperature and thermal stress fields of through-silicon-via (TSV) arrays in 3-D integrated circuits (ICs) based on a coupled-field finite-element (FE) method. The heat source under consideration is the active device layers of the ICs that are operating under load. Individual and combined effects of TSV array parameters, including TSV height, diameter, spacing, and array size, on die temperature and thermal stress are predicted. Good linear relationships are identified between the proposed TSV array parameters and predicted temperature and thermal stress fields of the ICs. A 3-D FE model of two-stack field-programmable gate arrays with an embedded TSV array has been built and validated with an analytical model and verified by experimental measurements.