A numerical model of an inter-strata liquid cooling solution for a 3D IC architecture

The advancement of contemporary three dimensional integrated circuit (3D IC) technologies offers a promising solution for the insatiable demand of the consumer electronics market. The increased complexity of 3D IC design permits the execution of multiple applications at greater speeds whilst remaining within the design constraints of energy consumption, yield and time-to-market. However, the increased computing performance and compact size may introduce a thermal barrier inhibiting performance, particularly in the case where multiple logic dies are stacked and co-aligned hot spots are induced. To mitigate this thermal barrier a novel integrated active thermal solution is investigated in this paper whose purpose is to alleviate hot spots in a contemporary two-die 3D IC architecture. The solution employs a series of integrated microchannels, interconnected through each stratum by through silicon fluidic vias (TSFVs), and permits the transfer of heat, via a coolant, from hot to cold zones. This microfluidic system is driven by an integrated AC electrokinetic pump embedded in the channel walls. Recent advancements in electrokinetic micropump technology have allowed greater increases in fluid velocity (mm/s) while operating within the voltage constraints of a 3D IC. Numerically qualitative and quantitative temperature distributions are presented for a contemporary in-house 3D IC chip both with and without microchannels for a local hot spot on the active layer of each silicon chip. Local co-aligned hot spot fluxes are investigated in the range 10W/cm
²
≤q"≤1000W/cm
²
. The internal 1D thermal profile is presented for each silicon die in the chip interface where temperature reduction of up to 20% is observed.