Combinational ATPG acceleration by dynamic circuit partition

If no FOS exists in the circuit under test, the execution time of DTM and STM linearly increase proportional to circuit size. The non-linear factors in the algorithm are introduced by FOSs. To limit the affection of FOS's as small as possible, a technique called Dynamic Search Space Reduction is introduced in this paper and only the FOSs who have more then two branches in the sensitive region have to be considered. The number of these FOSs usually very small because some of FOSs have been isolated by the search space reduction algorithm. In the meantime, we notice that the faults behind an FOS with two or more branches in the sensitive region are always testable if the fault can be propagate to the FOS without modify the associate line values along the sensitive paths.