A GaAs 1:8 demultiplexer on 1 K-gates GaAs gate array

A GaAs 1:8 demultiplexer was designed on 1 K gate GaAs gate array. The 1 K gate array employed 1.0 /spl mu/ m gate length MESFET on 2-inch GaAs wafers using TiPtAu gate recessed gate process. The basic logic cell in 1 K gate array utilized modified Schottky diode FET Logic (SDFL) which could constitute either 4NOR gate or 2NOR/2NAND gate circuit. The unloaded gate delay time of the basic cell was less than 200 ps with power dissipation less than 2 mW. The input and output level were compatible to Si ECL logic level. The chip size was 5.0/spl times/5.0 mm/sup 2/. The 1:8 demultiplexer was designed to be able to operate up to 500 MHz clock frequency with power dissipation less than 2.5 W.