Design for testability, placement and routing of a new oversampled /spl Sigma/-/spl Delta/ modulator

A new top-down design method is proposed in this paper including Verilog hardware description, synthesis, design for testability, library preparation, automatic placement and routing with some artificial interference using a new oversampled /spl Sigma/-/spl Delta/ modulator as an example. A theorem is also introduced for DFT consideration.