Design of a high speed cascaded sigma-delta ADC

A high speed /spl Sigma//spl Delta/ ADC is designed for video application. A multi-bit cascaded /spl Sigma//spl Delta/ modulator is used to gain additional resolution under the oversampling rate of 4 or 8. Quantization errors are analyzed. Multi-stage halfband filters are used to remove the quantization error out of the base band. Simulation results are included.