ASICs design for an MTD radar

In an MTD (Moving Target Detect) radar, the digital signal processing is implemented by some real-time processing pipelines which consist of ASICs and FIFO or dual-port memory. We designed six ASICs with Xilinx FPGA, including the clutter-map unit former, the moving target signal extractor, the video signal integrator and the CFAR (Constant False Alarm Rate) operator. While all the timing and control are also realized by FPGA. With these ASICs, the system becomes small, efficient, easy to debug and now is working successfully in practical applications.