A new method to evaluate effectiveness of CDM ESD protection

A new methodology for evaluating the effectiveness of CDM protection is presented. VFTLP measurements are performed on structures composed of an ESD protection device in parallel with a gate monitor device; a MOS transistor or inverter. Parametric shifts in threshold voltage, V
TH
, as well as drain saturation current, I
DD
, of the MOS monitor device are measured to continuously gauge the extent of the damage resulted from a CDM-like fast transient.