A new ESD design methodology for high voltage DMOS applications

A comprehensive methodology for synthesizing robust ESD performance in highly sensitive high voltage NLDMOS functional blocks is introduced. Optimizing high voltage output stage design for robust device- and system-level (IEC 61000-4-2)/HMM is assessed under 1-, 2-, 5-, 10-, 100-ns wide time frames of typical electrostatic discharge (ESD) stress models.