System level analysis and experimental characterization of frequency pulling in PLLs

In this paper a system-level experimental characterization and analysis of pulling in phase-locked-loops (PLL) is presented. Competitive effects originating from integrated IC (chip-level) through the PLL loop and the power amplifier (PA) are investigated taking into account coupling with SAW filter on PCB-level. Physical interpretation of observed pulling effects which result from combined influences of PLL loop, PA block and SAW filter module are proposed to sustain a global behavioral modeling using Matlab Simulink facilities, and Cadence Verilog-AMS tooling.