Congestion-aware Network-on-Chip router architecture

This paper proposes a novel congestion-aware Network-on-Chip (NoC) architecture that not only enhances network transmission performance while maintaining a feasible implementation cost, but also improves overall network throughput in various traffic scenarios. This congestion control scheme which consists of dynamic input arbitration and adaptive routing path selection is proposed to balance traffic load distribution so as to alleviate congestion caused by heavy network activities. Simulation results show that throughput is improved dramatically while maintaining superior latency performance for various traffic patterns. Cost evaluation results also show that congestion-aware router requires negligible cost overhead but provides better throughput for both mesh and diagonally-linked mesh NoC platforms.