COLK cell : A new embedded DRAM architecture for advanced CMOS nodes

This paper deals with a new and low cost embedded DRAM (eDRAM) architecture. COLK (Capacitor Over Low K) cell with capacitor placed in the first and thick SiO
₂
dielectric has been successfully integrated. 4Mb eDRAM testchip using this new architecture is functional in 45 nm node and presents good yield. Moreover we succeed to demonstrate the capability to continue downscaling of eDRAM for nodes down to 32 nm and 22nm.