HVM performance validation and DFM techniques used in a 32nm CMOS thermal sensor system

This paper describes the design of a 1.2-mW, 0.027-mm
²
thermal sensor and its accompanying supply voltage regulator, both implemented in a Hi-K, metal gate, 32nm technology. The designs incorporated built-in run-time variability reduction schemes for improved manufacturability, which allowed the sensor to achieve an INL of ±0.27°C over the operating range of 0°C to 110°C while the regulator met all functional specifications and introduced no additional yield loss. The DFT circuits needed to validate circuit performance in high volume manufacturing (HVM) are also described.