Verifying electrical/thermal/thermo-mechanical behavior of a 3D stack - Challenges and solutions

We describe the design challenges for a low-cost 130nm 3D CMOS technology with 5μm diameter at 10μm pitch Cu-TSV. We investigate electrical, thermal and thermo-mechanical issues encountered in 3D. The electrical yield and ESD of TSVs is reviewed and designers are advised how to ensure yield and reliability. For thermal and thermo-mechanical we'll indicate based on experimental characterization, the importance of extending the chip package co-design flow with thermo-mechanical simulations of the chip stack. We propose a new design flow which leverages information captured by smart samples.