Low power IEEE 802.15.4a UWB digital Rx baseband architecture

This paper presents a low power ultra-wide band digital receiver baseband architecture for handling IEEE 802.15.4a packets in real-time. Real-time processing allows duty cycling of the analog frontend, which is key to achieve low power consumption. The architecture consists of a programmable application specific instruction set processor and a set of application specific integrated circuits. The design is split up into multiple clock domains to meet timing requirements of up to 499.2MHz. The architecture runs in real-time on FPGA, and is synthesizable for 90nm CMOS at 0.84V. This results in a low power flexible C programmable baseband architecture, which is ideal for algorithm development and tuning.