Interblock memory for turbo trellis coded modulation

This paper presents a turbo trellis coded modulation (TTCM) scheme for which the encoding is implemented by serially concatenating a demultiplexer, a multilevel delay processor, and a signal mapper to the encoder of a binary turbo code. Through the delay processor and the signal mapper, interblock memory is introduced between consecutive binary turbo codewords. The proposed TTCM can be decoded based on the demapper and the binary turbo decoder. We can design a TTCM with a rate of 2 bits per 8PSK symbol and a pinch-off limit of 3.08 dB which is only 0.18 dB away from the capacity (2.9 dB).