Real-time image encryption based chaotic synchronized embedded cryptosystems

This paper proposes a new and efficient way to deal with the chaotic synchronization for embedded hardware cryptosystems and its FPGA implementation for designing a real time image secure symmetric encryption scheme. The implementation and experimental results mapped on two Xilinx FPGA Virtex technology platforms demonstrate the feasibility and the usefulness of our secure solution. The originality of this new scheme is that it allows a low cost image encryption for embedded systems while still providing a good trade-off between performance and hardware resources. Thorough experimental tests are carried out with detailed analysis, demonstrating the high security and fast encryption speed of the new scheme while still able to resist statistical analysis attack.