A 0.5 mm$^{2}$ Power-Scalable 0.5–3.8-GHz CMOS DT-SDR Receiver With Second-Order RF Band-Pass Sampler

A highly flexible receiver chain based on RF-sampling and discrete-time signal processing in the charge domain for SDR applications is presented. A compact switched-inductor variable-gain front-end provides multiband low noise amplification and RF-selectivity with reduced area penalties. Strong selectivity at RF was obtained through a novel discrete-time decimating bandpass filter with triangular weighted filter taps. Decimation filters with programmable number of taps offer flexible rate decimation. A power scalable discrete-time baseband filter was implemented in-order to minimize static power consumption. The 90-nm digital CMOS implementation achieves a noise figure of 5.1 dB, a variable gain range of more than 60 dB with +1 dBm IIP3 and +50 dBm IIP2. This is achieved for power figures competitive with dedicated solutions. The receiver, frequency synthesizer excluded, occupies only 0.5 mm
²
.