Bulk-driven Flipped Voltage Differential Pair

This paper explores a new design approach of a low-power high slew rate CMOS voltage buffer. The buffer is based on the Flipped Voltage Follower Pseudo Differential Pair, but the bulk-driven technique is utilized at the input stage to achieve rail-to-rail operation. This buffer has been designed for a 0.35μm CMOS technology to operate at a 1.8V supply voltage. The BSIM3 simulated results are provided which demonstrate the open-loop gain of 50dB, gain bandwidth of 3MHz with a 5pF load, whereas the total static current consumption remains below 9μA. This paper also addresses the issue of latch-up problem that occurs with a large step input.